Module Handbook

  • Dynamischer Default-Fachbereich geändert auf INF

Module INF-62-01-M-5

Processor Architecture (M, 4.0 LP)

Module Identification

Module Number Module Name CP (Effort)
INF-62-01-M-5 Processor Architecture 4.0 CP (120 h)


CP, Effort 4.0 CP = 120 h
Position of the semester 1 Sem. in WiSe
Level [5] Master (Entry Level)
Language [EN] English
Module Manager
Area of study [INF-ES] Embedded Systems and Robotics
Reference course of study [INF-88.79-SG] M.Sc. Computer Science
Livecycle-State [NORM] Active


Type/SWS Course Number Title Choice in
Presence-Time /
SL SL is
required for exa.
PL CP Sem.
2V+1U INF-62-01-K-5
Processor Architecture
P 42 h 78 h
ja PL1 4.0 WiSe
  • About [INF-62-01-K-5]: Title: "Processor Architecture"; Presence-Time: 42 h; Self-Study: 78 h
  • About [INF-62-01-K-5]: The study achievement "[U-Schein] proof of successful participation in the exercise classes (ungraded)" must be obtained.
    • It is a prerequisite for the examination for PL1.

Examination achievement PL1

  • Form of examination: oral examination (15-30 Min.)
  • Examination Frequency: irregular (by arrangement)
  • Examination number: 66201 ("Processor Architecture")

Evaluation of grades

The grade of the module examination is also the module grade.


  • Computer arithmetics for parallel instruction execution
  • Generalization of pipeline processing
  • Processors with dynamic scheduling (superscalarity)
  • Processors with static scheduling (VLIW/DSP)
  • Vector computer and vectorization of code
  • application specific processors

Competencies / intended learning achievements

Upon successful completion of the module, students will be able to
  • explain the microarchitecture of current processor architectures,
  • explain the interaction of its components,
  • explain the interaction of processors and compilers,
  • explain the parallelization of sequential programs at command level,
  • classify new developments of application-specific processors.


  • J.A. Fisher, P. Faraboschi and C. Young; Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools; Morgan Kaufmann
  • B. Parhami; Computer Architecture: From Microprocessors to Supercomputers; Oxford University Press, 2005
  • M. Lu; Arithmetic and Logic in Computer Systems; Wiley Interscience, 2004
  • H. El-Rewini, M. Abd-El-Barr; Advance Computer Architecture and Parallel Processing; Wiley, 2005
  • T. Ungerer; Parallelrechner und parallele Programmierung; Spektrum Verlag, 1997
  • J.L. Hennessy and D.A. Patterson; Computer Organization and Design - A Quantitative Approach; Morgan Kaufmann Publishers, 2007
  • K. Hwang; Computer Arithmetic, Principles, Architecture and Design; John Wiley and Sons; 1979

Requirements for attendance of the module (informal)


Requirements for attendance of the module (formal)


References to Module / Module Number [INF-62-01-M-5]

Course of Study Section Choice/Obligation
[INF-88.79-SG] M.Sc. Computer Science [Specialisation] Specialization 1 [WP] Compulsory Elective
Module-Pool Name
[GS-CVT-CS-2022-E-MPOOL-6] Catalog Electives Computer Science 2022
[GS-CVT-CS-E-MPOOL-6] Catalog Electives Computer Science
[INF-ES_Ba_V-MPOOL-4] Specialization Bachelor TA Embedded Systems and Robotics
[MV-MB-INF-2022-MPOOL-6] Wahlpflichtmodule M.Sc. Maschinenbau mit angewandter Informatik 2022
[MV-MBINFO-MPOOL-6] Wahlpflichtmodule Maschinenbau mit angewandter Informatik