- Manufacturing technologies and -methods for integrated circuits (CMOS (bulk, SOI), BiCMOS)
- Device spectrum, process variations, yield, tolerances and soft-faults
- Principles of layout-design for analog and mixed-signal circuits (matched-layout)
- Design methodology and tools of computer-aided design for integrated mixed-signal electronics (Hierarchical design, mixed-mode, mixed-signal, AHDLs)
- Simple (SPICE-level 1) and advanced device models (e.g., BSIM-models)
- Rehearsal of basic circuits & building blocks for integrated analog electronics (References etc.)
- Design techniques for applications-specific cells and blocks: selection, sizing, simulation, layout, extraction, post-layout simulation for application-specific (single-ended and fully-differential) operational amplifiers (OpAmp/OTA), RC-, GmC-, SC-Filters, AD/DA-converters, VCO etc.
- Extension to analysis of temperature drift and statistical influence from manufacturing tolerances (parametric, Monte-Carlo, and corner analysis etc.)
- Modeling, design and layout realization of digital circuits as components in integrated mixed-signal electronics, related signal integrity issues
- Advanced issues: Noise, analog synthesis, testing, reconfiguration, eigen- or self calibration, self-monitoring/-repair, adaptation
Technology and Design of Integrated Mixed-Signal Circuits and Systems (TESYS) (M, 5.0 LP)
|Module Number||Module Name||CP (Effort)|
|EIT-ISE-651-M-4||Technology and Design of Integrated Mixed-Signal Circuits and Systems (TESYS)||5.0 CP (150 h)|
|CP, Effort||5.0 CP = 150 h|
|Position of the semester||1 Sem. in SuSe|
|Level|| Bachelor (Specialization)|
|Area of study||[EIT-ISE] Integrated Sensor Systems|
|Type/SWS||Course Number||Title||Choice in |
|SL||SL is |
required for exa.
Technology and Design of Integrated Mixed-Signal Circuits and Systems (TESYS)
|P||56 h||94 h||
- About [EIT-ISE-651-K-4]: Title: "Technology and Design of Integrated Mixed-Signal Circuits and Systems (TESYS)"; Presence-Time: 56 h; Self-Study: 94 h
- About [EIT-ISE-651-K-4]:
The study achievement "[PROJ-Schein] proof of successful completion of the project(s)" must be obtained.
- It is a prerequisite for the examination for PL1.
Examination achievement PL1
- Form of examination: oral examination (30 Min.)
- Examination Frequency: each semester
Evaluation of grades
The grade of the module examination is also the module grade.
From [EIT-ISE-651-K-4] Technology and Design of Integrated Mixed-Signal Circuits and Systems (TESYS):
Competencies / intended learning achievements
After completing this module you can...
- ... explain the employed manufacturing processes, the related device spectra, methods, description approaches, and tools for the computer-aided modeling, simulation and manufacturing of integrated analog and mixed-signal circuits.
- ... master the Cadence DFW II IC design system and a common manufacturing technology (CMOS, BiCMOS), and design-kit (mixed-mode, mixed-signal).
- ... explain common analog and mixed-signal-circuits and building blocks, their properties, and to properly choose for an application in a front-to-back design (physical validated cell/system layout).
- ... select suitable circuit topology (from lecture or from publications, e.g., accessable by IEEEexplore) and achieve a proper sizing of the circuit for the given manufacturing technology and the application specification.
- ... design a matched circuit/cell layout of the sized cirucit under area and power constraints.
- ... combine custom cells with cells from analog and/or digital cell libraries of the manufacturer or design group members to more complex designs.
- ... basically design chip core and pad frame in the context of a properly chosen chip package, and stream out the final validated design (GDS-II).
- ... realize independently a design project or a sub-project in the context of a larger group design (MPC on MPW), preferably with relation to ISE research in intelligent sensor systems and neural systems.
Requirements for attendance of the module (informal)
- [EIT-ISE-105-M-2] Electrical Measurement Technique I (M, 4.0 LP)
- [EIT-ISE-701-M-2] Electronics I (M, 6.0 LP)
- [EIT-ISE-702-M-3] Electronics II (M, 4.0 LP)
Requirements for attendance of the module (formal)None
References to Module / Module Number [EIT-ISE-651-M-4]
|Course of Study||Section||Choice/Obligation|
|[EIT-82.781-SG#2019] B.Sc. Electrical and Computer Engineering ||[Specialisation] Major-Specific Advanced Subjects||[P] Compulsory|
|[EIT-82.781-SG#2019] B.Sc. Electrical and Computer Engineering ||[Free Elective Area] Elective Subjects||[W] Elective Module|
|[EIT-88.A20-SG#2021] M.Sc. European Master in Embedded Computing Systems (EMECS) ||[Free Elective Area] Elective Subjects||[W] Elective Module|
|[EIT-88.D55-SG#2021] M.Sc. Embedded Computing Systems (ESY) ||[Free Elective Area] Elective Subjects||[W] Elective Module|
|[EIT-EIT-BSC-TW-MPOOL-4]||Technical Elective Modules Bachelor EIT|
|[EIT-SIAK-DT-ENG-MPOOL]||SIAK Certificate "Digital Transformation" - Modules EIT "Engineering"|
|[GS-CVT-EE-2022-E-MPOOL-6]||Catalog Electives Electrical and Computer Engineering 2022|
|[GS-CVT-EE-E-MPOOL-6]||Catalog Electives Electrical and Computer Engineering|