- VHDL simulation model
- VHDL language patterns for synthesis
- VHDL language patterns for validation
- Number representation and arithmetics in hardware
- Overview of target technologies
- Exercises and design of a DCF77 signal decoder
Module EIT-EMS-742-M-7
Implementation of Integrated Circuits (M, 2.0 LP)
Module Identification
Module Number | Module Name | CP (Effort) |
---|---|---|
EIT-EMS-742-M-7 | Implementation of Integrated Circuits | 2.0 CP (60 h) |
Basedata
CP, Effort | 2.0 CP = 60 h |
---|---|
Position of the semester | 1 Sem. in WiSe/SuSe |
Level | [7] Master (Advanced) |
Language | [EN] English |
Module Manager | |
Lecturers | |
Area of study | [EIT-EMS] Microelectronic Systems Design |
Reference course of study | [EIT-88.781-SG#2010] M.Sc. Electrical and Computer Engineering [2010] |
Livecycle-State | [NORM] Active |
Courses
Type/SWS | Course Number | Title | Choice in Module-Part | Presence-Time / Self-Study | SL | SL is required for exa. | PL | CP | Sem. | |
---|---|---|---|---|---|---|---|---|---|---|
2L | EIT-EMS-742-K-7 | Implementation of Integrated Circuits
| P | 28 h | 32 h |
L-Schein
| ja | PL1 | 2.0 | WiSe/SuSe |
- About [EIT-EMS-742-K-7]: Title: "Implementation of Integrated Circuits"; Presence-Time: 28 h; Self-Study: 32 h
- About [EIT-EMS-742-K-7]: The study achievement [L-Schein] proof of successful participation in the practical course / lab must be obtained. It is a prerequisite for the examination for PL1.
Examination achievement PL1
- Form of examination: written exam (Klausur) (60-90 Min.)
- Examination Frequency: each semester
Evaluation of grades
The module is not graded.
Contents
Competencies / intended learning achievements
After completing this module you can...
- ... design combinatorial and sequential circuits on register-transfer-level.
- ... design sequential circuits appropriate for synthesis tools.
- ... employ state-of-the-art EDA tools for design and validation of digital circuits.
- ... assess and judge various target technologies for a design.
Requirements for attendance (informal)
Modules:
- [EIT-EIS-314-M-2] Fundamentals of Information Processing (M, 6.0 LP)
- [EIT-EIS-571-M-4] Architecture of Digital Systems I (M, 4.0 LP)
Requirements for attendance (formal)
None
References to Module / Module Number [EIT-EMS-742-M-7]
Course of Study | Section | Choice/Obligation |
---|---|---|
[EIT-88.781-SG#2010] M.Sc. Electrical and Computer Engineering [2010] | Elective Subjects | [W] Elective Module |
[EIT-88.A44-SG#2018] M.Sc. Media and Communication Technology [2018] | Technical Elective Subjects | [W] Elective Module |
[EIT-88.?-SG#2021] M.Sc. Electrical and Computer Engineering [2021] | Technical Elective Modules | [W] Elective Module |
[EIT-88.?-SG#2021] M.Sc. Media and Communication Technology [2021] | Technical Elective Modules | [W] Elective Module |