Module Handbook

  • Dynamischer Default-Fachbereich geändert auf EIT

Module EIT-EMS-659-M-7

SystemC and Virtual Prototyping (M, 4.0 LP)

Module Identification

Module Number Module Name CP (Effort)
EIT-EMS-659-M-7 SystemC and Virtual Prototyping 4.0 CP (120 h)

Basedata

CP, Effort 4.0 CP = 120 h
Position of the semester 1 Sem. in WiSe
Level [7] Master (Advanced)
Language [EN] English
Module Manager
Lecturers
Area of study [EIT-EMS] Microelectronic Systems Design
Livecycle-State [NORM] Active

Courses

Type/SWS Course Number Title Choice in
Module-Part
Presence-Time /
Self-Study
SL SL is
required for exa.
PL CP Sem.
2V+1U EIT-EMS-659-K-7
SystemC and Virtual Prototyping
P 42 h 78 h - - PL1 4.0 WiSe
  • About [EIT-EMS-659-K-7]: Title: "SystemC and Virtual Prototyping"; Presence-Time: 42 h; Self-Study: 78 h

Examination achievement PL1

  • Form of examination: written exam (Klausur) (90 Min.)
  • Examination Frequency: each semester

Evaluation of grades

The grade of the module examination is also the module grade.


Contents

Today's companies have to deal with complex hardware architectures such as heterogeneous multi-core systems. Therefore, new development tools and approaches such as virtual prototyping are needed for efficient and fast design on electronic system level. In our research, we use SystemC and gem5 based virtual platforms for a thorough design space exploration on software and hardware level.
  • Introduction to virtual prototyping and virtual product development methodology for embedded systems
  • System models and specification
  • Hardware/Software co-development with virtual prototyping
  • Modelling with cycle accurate SystemC
  • Modelling on higher level of abstraction with Transaction Level Modeling (TLM)
  • Modelling of embedded processors with gem5
  • Design space exploration for embedded systems with virtual prototypes

Competencies / intended learning achievements

After completing this module you can...
  • ... explain advantages of novel virtual product development.
  • ... find the right level of abstraction for a specific problem.
  • ... reason about the tradeoff between accuracy and simulation speed.
  • ... use virtual platforms for hardware/software co-development and design space exploration.

Requirements for attendance (informal)

Know-how about computer architecture (e.g. ADS1, Assembler Programming), RTL hardware design (VHDL, Verilog), basic programming skills in C and object oriented C++, Version control systems (git).

Requirements for attendance (formal)

None

References to Module / Module Number [EIT-EMS-659-M-7]

Course of Study Section Choice/Obligation
[EIT-88.A20-SG#2021] M.Sc. European Master in Embedded Computing Systems (EMECS) [2021] Elective Subjects [W] Elective Module
[EIT-88.?-SG#2021] M.Sc. Embedded Computing Systems (ESY) [2021] Elective Subjects [W] Elective Module
Module-Pool Name
[EIT-AUT-CAS-WP-MPOOL-7] CAS Core Electives