-
Data representation
- Signed and unsigned fixed point numbers
- Floating point numbers, IEEE 754 standard
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Computer arithmetic
- Algorithms
- Sequential and parallel hardware implementations
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Instruction set and machine language
- Instruction set categories
- Addressing modes
- Assembler programming
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Data path and control
- Hardware implementation of a processor
- Control unit design, microprogramming
- Exceptions
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Instruction-level parallelism
- Pipelining
- Superscalar and VLIW processors
- Dynamic scheduling
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Memory hierarchy
- Caches
- Virtual memory, page tables, TLB
Module EIT-EIS-571-M-4
Architecture of Digital Systems I (M, 4.0 LP)
Module Identification
| Module Number | Module Name | CP (Effort) |
|---|---|---|
| EIT-EIS-571-M-4 | Architecture of Digital Systems I | 4.0 CP (120 h) |
Basedata
| CP, Effort | 4.0 CP = 120 h |
|---|---|
| Position of the semester | 1 Sem. in WiSe |
| Level | [4] Bachelor (Specialization) |
| Language | [EN] English |
| Module Manager | |
| Lecturers | |
| Area of study | [EIT-EIS] Electronic Design Automatization |
| Livecycle-State | [NORM] Active |
Courses
| Type/SWS | Course Number | Title | Choice in Module-Part | Presence-Time / Self-Study | SL | SL is required for exa. | PL | CP | Sem. | |
|---|---|---|---|---|---|---|---|---|---|---|
| 2V+1U | EIT-EIS-571-K-4 | Architecture of Digital Systems I
| P | 42 h | 78 h | - | - | PL1 | 4.0 | WiSe |
- About [EIT-EIS-571-K-4]: Title: "Architecture of Digital Systems I"; Presence-Time: 42 h; Self-Study: 78 h
Examination achievement PL1
- Form of examination: oral examination (30 Min.)
- Examination Frequency: each semester
Evaluation of grades
The grade of the module examination is also the module grade.
Contents
Competencies / intended learning achievements
After completing this module you can...
- ... identify and describe a RISC instruction set architecture (ISA) for embedded processors.
- ... explain the purpose, working principles and interrelation of the components of an embedded processor core.
- ... relate features of the ISA to internal structures of the processor hardware.
- ... classify and explain principles of instruction level parallelism.
- ... explain the working principles, general architecture of a processor’s memory hierarchy.
- ... devise the general hardware for embedded processors at the block diagram level.
Requirements for attendance (informal)
Modules:
Requirements for attendance (formal)
None