Module Handbook

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Module EIT-EIS-571-M-4

Architecture of Digital Systems I (M, 4.0 LP)

Module Identification

Module Number Module Name CP (Effort)
EIT-EIS-571-M-4 Architecture of Digital Systems I 4.0 CP (120 h)

Basedata

CP, Effort 4.0 CP = 120 h
Position of the semester 1 Sem. in WiSe
Level [4] Bachelor (Specialization)
Language [EN] English
Module Manager
Lecturers
Area of study [EIT-EIS] Electronic Design Automatization
Livecycle-State [NORM] Active

Courses

Type/SWS Course Number Title Choice in
Module-Part
Presence-Time /
Self-Study
SL SL is
required for exa.
PL CP Sem.
2V+1U EIT-EIS-571-K-4
Architecture of Digital Systems I
P 42 h 78 h - - PL1 4.0 WiSe
  • About [EIT-EIS-571-K-4]: Title: "Architecture of Digital Systems I"; Presence-Time: 42 h; Self-Study: 78 h

Examination achievement PL1

  • Form of examination: oral examination (30 Min.)
  • Examination Frequency: each semester

Evaluation of grades

The grade of the module examination is also the module grade.


Contents

  • Data representation
    • Signed and unsigned fixed point numbers
    • Floating point numbers, IEEE 754 standard
  • Computer arithmetic
    • Algorithms
    • Sequential and parallel hardware implementations
  • Instruction set and machine language
    • Instruction set categories
    • Addressing modes
    • Assembler programming
  • Data path and control
    • Hardware implementation of a processor
    • Control unit design, microprogramming
    • Exceptions
  • Instruction-level parallelism
    • Pipelining
    • Superscalar and VLIW processors
    • Dynamic scheduling
  • Memory hierarchy
    • Caches
    • Virtual memory, page tables, TLB

Competencies / intended learning achievements

After completing this module you can...
  • ... identify and describe a RISC instruction set architecture (ISA) for embedded processors.
  • ... explain the purpose, working principles and interrelation of the components of an embedded processor core.
  • ... relate features of the ISA to internal structures of the processor hardware.
  • ... classify and explain principles of instruction level parallelism.
  • ... explain the working principles, general architecture of a processor’s memory hierarchy.
  • ... devise the general hardware for embedded processors at the block diagram level.

Requirements for attendance (informal)

Modules:

Requirements for attendance (formal)

None

References to Module / Module Number [EIT-EIS-571-M-4]

Course of Study Section Choice/Obligation
[EIT-82.781-SG#2019] B.Sc. Electrical and Computer Engineering [2019] Major-Specific Advanced Subjects [P] Compulsory
[EIT-82.781-SG#2019] B.Sc. Electrical and Computer Engineering [2019] Major-Specific Advanced Subjects [P] Compulsory
[EIT-88.781-SG#2010] M.Sc. Electrical and Computer Engineering [2010] Specialization Modules [P] Compulsory
[EIT-88.A44-SG#2018] M.Sc. Media and Communication Technology [2018] Technical Elective Subjects [W] Elective Module
[EIT-82.?-SG#2021] B.Sc. Electrical and Computer Engineering [2021] Major-Specific Advanced Subjects [P] Compulsory
[EIT-82.?-SG#2021] B.Sc. Media and Communication Technology [2021] Technical Elective Modules [W] Elective Module
[EIT-88.?-SG#2021] M.Sc. Media and Communication Technology [2021] Technical Elective Modules [W] Elective Module
[EIT-88.A20-SG#2021] M.Sc. European Master in Embedded Computing Systems (EMECS) [2021] Core Subjects [WP] Compulsory Elective
[EIT-88.?-SG#2021] M.Sc. Automation and Control (A&C) [2021] Elective Modules [W] Elective Module
[EIT-88.?-SG#2021] M.Sc. Embedded Computing Systems (ESY) [2021] Core Program [WP] Compulsory Elective
Module-Pool Name
[EIT-AUT-CAS-WP-MPOOL-7] CAS Core Electives
[GS-CVT-EE-E-MPOOL-6] Catalog Electives Electrical and Computer Engineering