Module Handbook

  • Dynamischer Default-Fachbereich geändert auf INF

Course INF-62-01-K-5

Processor Architecture (2V+1U, 4.0 LP)

Course Type

SWS Type Course Form CP (Effort) Presence-Time / Self-Study
- K Lecture with exercise classes (V/U) 4.0 CP 78 h
2 V Lecture 28 h
1 U Exercise class (in small groups) 14 h
(2V+1U) 4.0 CP 42 h 78 h

Basedata

SWS 2V+1U
CP, Effort 4.0 CP = 120 h
Position of the semester 1 Sem. in WiSe
Level [5] Master (Entry Level)
Language [EN] English
Lecturers
Area of study [INF-ES] Embedded Systems and Robotics
Livecycle-State [NORM] Active

Possible Study achievement

  • Verification of study performance: proof of successful participation in the exercise classes (ungraded)
  • Details of the examination (type, duration, criteria) will be announced at the beginning of the course.

Contents

  • Computer arithmetics for parallel instruction execution
  • Generalization of pipeline processing
  • Processors with dynamic scheduling (superscalarity)
  • Processors with static scheduling (VLIW/DSP)
  • Vector computer and vectorization of code
  • application specific processors

Literature

  • J.A. Fisher, P. Faraboschi and C. Young; Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools; Morgan Kaufmann
  • B. Parhami; Computer Architecture: From Microprocessors to Supercomputers; Oxford University Press, 2005
  • M. Lu; Arithmetic and Logic in Computer Systems; Wiley Interscience, 2004
  • H. El-Rewini, M. Abd-El-Barr; Advance Computer Architecture and Parallel Processing; Wiley, 2005
  • T. Ungerer; Parallelrechner und parallele Programmierung; Spektrum Verlag, 1997
  • J.L. Hennessy and D.A. Patterson; Computer Organization and Design - A Quantitative Approach; Morgan Kaufmann Publishers, 2007
  • K. Hwang; Computer Arithmetic, Principles, Architecture and Design; John Wiley and Sons; 1979

Requirements for attendance (informal)

Courses

Requirements for attendance (formal)

None

References to Course [INF-62-01-K-5]

Module Name Context
[INF-62-01-M-5] Processor Architecture P: Obligatory 2V+1U, 4.0 LP
Course-Pool Name
[INF-ES_V-KPOOL-6] Lectures of the teaching area Embedded Systems and Robotics