Module Handbook

  • Dynamischer Default-Fachbereich geändert auf EIT

Course EIT-EMS-659-K-7

SystemC and Virtual Prototyping (2V+1U, 4.0 LP)

Course Type

SWS Type Course Form CP (Effort) Presence-Time / Self-Study
- K Lecture with exercise classes (V/U) 4.0 CP
2 V Lecture 28 h 48 h
1 U Lecture hall exercise class 14 h 30 h
(2V+1U) 4.0 CP 42 h 78 h


CP, Effort 4.0 CP = 120 h
Position of the semester 1 Sem. in WiSe
Level [7] Master (Advanced)
Language [EN] English
Area of study [EIT-EMS] Microelectronic Systems Design
Livecycle-State [NORM] Active


Today's companies have to deal with complex hardware architectures such as heterogeneous multi-core systems. Therefore, new development tools and approaches such as virtual prototyping are needed for efficient and fast design on electronic system level. In our research, we use SystemC and gem5 based virtual platforms for a thorough design space exploration on software and hardware level.
  • Introduction to virtual prototyping and virtual product development methodology for embedded systems
  • System models and specification
  • Hardware/Software co-development with virtual prototyping
  • Modelling with cycle accurate SystemC
  • Modelling on higher level of abstraction with Transaction Level Modeling (TLM)
  • Modelling of embedded processors with gem5
  • Design space exploration for embedded systems with virtual prototypes


  • SystemC: From the Ground Up ISBN: 978-0-387-69957-8 Springer
  • Modellierung von digitalen Systemen mit SystemC ISBN: 978-3-486-70581-2 Oldenbourg Verlag
  • IEEE Standard SystemC Reference Manual (LRM) IEEE


see OLAT

Requirements for attendance (informal)

Know-how about computer architecture (e.g. ADS1, Assembler Programming), RTL hardware design (VHDL, Verilog), basic programming skills in C and object oriented C++, Version control systems (git).

Requirements for attendance (formal)


References to Course [EIT-EMS-659-K-7]

Module Name Context
[EIT-EMS-659-M-7] SystemC and Virtual Prototyping P: Obligatory 2V+1U, 4.0 LP