Module Handbook

  • Dynamischer Default-Fachbereich geändert auf EIT

Course EIT-EMS-657-K-7

Synthesis and Optimization of Microelectronic Systems I (2V+1U, 4.0 LP)

Course Type

SWS Type Course Form CP (Effort) Presence-Time / Self-Study
- K Lecture with exercise classes (V/U) 4.0 CP
2 V Lecture 28 h 48 h
1 U Lecture hall exercise class 14 h 30 h
(2V+1U) 4.0 CP 42 h 78 h


CP, Effort 4.0 CP = 120 h
Position of the semester 1 Sem. in WiSe
Level [7] Master (Advanced)
Language [EN] English
Area of study [EIT-EMS] Microelectronic Systems Design
Livecycle-State [NORM] Active


  • System modeling and specification
  • HW/SW Codesign methodologies
  • Implementation platforms
  • Partitioning
  • Discrete optimization techniques e.g. simulated annealing, ILP
  • High-Level Synthesis, scheduling, allocation, binding
  • RT-synthesis, retiming


  • G. De Micheli: Snythesis and Optimization of Digital Circuits, Addison Wesley
  • D. Gajski: Introduction to High-Level Synthesis, Kluwer Academic Publisher


see OLAT

Requirements for attendance (informal)

Fundamentals of computer architecture and hardware design

Requirements for attendance (formal)


References to Course [EIT-EMS-657-K-7]

Module Name Context
[EIT-EMS-657-M-7] Synthesis and Optimization of Microelectronic Systems I P: Obligatory 2V+1U, 4.0 LP