Module Handbook

  • Dynamischer Default-Fachbereich geändert auf EIT

Course EIT-EMS-655-K-7

Microelectronic Circuit and System Design II (3V+1U, 5.0 LP)

Course Type

SWS Type Course Form CP (Effort) Presence-Time / Self-Study
- K Lecture with exercise classes (V/U) 5.0 CP
3 V Lecture 42 h 64 h
1 U Lecture hall exercise class 14 h 30 h
(3V+1U) 5.0 CP 56 h 94 h

Basedata

SWS 3V+1U
CP, Effort 5.0 CP = 150 h
Position of the semester 1 Sem. in SuSe
Level [7] Master (Advanced)
Language [EN] English
Lecturers
Area of study [EIT-EMS] Microelectronic Systems Design
Livecycle-State [NORM] Active

Contents

  • Analysis and optimization of power/energy in microelectronic circuits and systems
  • Interconnect in advanced technology nodes
  • Timing issues and optimization
  • Network-on-Chip architectures
  • Techniques to increase throughput
  • Memory Architectures
  • 3D integration

Literature

  • J. M. Rabaey : Digital Integrated Circuits - A Design Perspective, Prentice Hall
  • P. Veendrick: Deep-Submicron CMOS ICs: From Basics to ASICs, Kluwer Academic Publisher
  • C. Rowen: Engineering the Complex SoCs, Prentice Hall

Materials

see OLAT

Requirements for attendance (informal)

Modules:

Requirements for attendance (formal)

None

References to Course [EIT-EMS-655-K-7]

Module Name Context
[EIT-EMS-655-M-7] Microelectronic Circuit and System Design II P: Obligatory 3V+1U, 5.0 LP