Module Handbook

  • Dynamischer Default-Fachbereich geändert auf EIT

Course EIT-EIS-571-K-4

Architecture of Digital Systems I (2V+1U, 4.0 LP)

Course Type

SWS Type Course Form CP (Effort) Presence-Time / Self-Study
- K Lecture with exercise classes (V/U) 4.0 CP
2 V Lecture 28 h 48 h
1 U Lecture hall exercise class 14 h 30 h
(2V+1U) 4.0 CP 42 h 78 h

Basedata

SWS 2V+1U
CP, Effort 4.0 CP = 120 h
Position of the semester 1 Sem. in WiSe
Level [4] Bachelor (Specialization)
Language [EN] English
Lecturers
Area of study [EIT-EIS] Electronic Design Automatization
Livecycle-State [NORM] Active

Contents

  • Data representation
    • Signed and unsigned fixed point numbers
    • Floating point numbers, IEEE 754 standard
  • Computer arithmetic
    • Algorithms
    • Sequential and parallel hardware implementations
  • Instruction set and machine language
    • Instruction set categories
    • Addressing modes
    • Assembler programming
  • Data path and control
    • Hardware implementation of a processor
    • Control unit design, microprogramming
    • Exceptions
  • Instruction-level parallelism
    • Pipelining
    • Superscalar and VLIW processors
    • Dynamic scheduling
  • Memory hierarchy
    • Caches
    • Virtual memory, page tables, TLB

Literature

  • Patterson; Hennessy: Computer Organization and Design - The Hardware/Software-Interface. Morgan Kaufmann, 2007
  • Hennessy; Patterson: Computer Architecture – A Quantitative Approach. Morgan Kaufmann, 2002

Materials

Lecture slides

Requirements for attendance (informal)

Modules:

Requirements for attendance (formal)

None

References to Course [EIT-EIS-571-K-4]

Module Name Context
[EIT-EIS-571-M-4] Architecture of Digital Systems I P: Obligatory 2V+1U, 4.0 LP