Course EIT-EIS-562-K-7
Semesterprojekt Verifikation Digitaler Systeme (2S, 3.0 LP)
Course Type
| SWS | Type | Course Form | CP (Effort) | Presence-Time / Self-Study | |
|---|---|---|---|---|---|
| 2 | S | Project seminar | 3.0 CP | 15 h | 75 h |
| (2S) | 3.0 CP | 15 h | 75 h | ||
Basedata
| SWS | 2S |
|---|---|
| CP, Effort | 3.0 CP = 90 h |
| Position of the semester | 1 Sem. in WiSe |
| Level | [7] Master (Advanced) |
| Language | [EN] English |
| Lecturers | |
| Area of study | [EIT-EIS] Electronic Design Automatization |
| Livecycle-State | [NORM] Active |
Contents
Methodik zur Verifikation eines System-on-Chip Moduls und ihre praktische Anwendung
Literature
wird in Vorlesung bekannt gegeben
Materials
kommerzielle Tools, wird in Vorlesung bekannt gegeben
Registration
elektronische Anmeldung erforderlich
Requirements for attendance (informal)
None
Requirements for attendance (formal)
only in combination with "Verification of Digital Systems"
References to Course [EIT-EIS-562-K-7]
| Module | Name | Context | |
|---|---|---|---|
| [EIT-EIS-562-M-7] | Class Project Verification of Digital Systems | P: Obligatory | 2S, 3.0 LP |