Course EIT-EIS-560-K-7
Verification of Digital Systems (4V, 5.0 LP)
Course Type
| SWS | Type | Course Form | CP (Effort) | Presence-Time / Self-Study | |
|---|---|---|---|---|---|
| 4 | V | Lecture with integrated exercises | 5.0 CP | 56 h | 94 h |
| (4V) | 5.0 CP | 56 h | 94 h | ||
Basedata
| SWS | 4V |
|---|---|
| CP, Effort | 5.0 CP = 150 h |
| Position of the semester | 1 Sem. in WiSe |
| Level | [7] Master (Advanced) |
| Language | [EN] English |
| Lecturers | |
| Area of study | [EIT-EIS] Electronic Design Automatization |
| Livecycle-State | [NORM] Active |
Contents
- Formal hardware verification in System-on-Chip design flow
- Graph representations of Boolean functions (BDDs, BMDs)
- CTL Model Checking
- Symbolic Model Checking
- Property checking with SAT-based methods (bounded model checking)
- Formal equivalence checking
- Industrial trends, scientific challenges
- Solving proactical verification problems with a commercial tool
Literature
- G. Hachtel, F. Somenzi: Logic Synthesis and Verification Algorithms, Kluwer Academic Publishers, 2010, ISBN 0-7923-9746-0.
- S. Hassoun and T. Sasao (Eds.) Logic Synthesis and Verification, Kluwer Academic Publishers, 2002. ISBN- 0-7923-7606-4.
Materials
- lecture slides
Registration
Mandatory registration for integrated lab
Requirements for attendance (informal)
Modules:
Requirements for attendance (formal)
None
References to Course [EIT-EIS-560-K-7]
| Module | Name | Context | |
|---|---|---|---|
| [EIT-EIS-560-M-7] | Verification of Digital Systems | P: Obligatory | 4V, 5.0 LP |