Module Handbook

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Course EIT-EIS-521-K-7

Embedded Systems Laboratory (4L, 5.0 LP)

Course Type

SWS Type Course Form CP (Effort) Presence-Time / Self-Study
4 L Laboratory course 5.0 CP 56 h 94 h
(4L) 5.0 CP 56 h 94 h

Basedata

SWS 4L
CP, Effort 5.0 CP = 150 h
Position of the semester 1 Sem. in WiSe
Level [7] Master (Advanced)
Language [EN] English
Lecturers
Area of study [EIT-EIS] Electronic Design Automatization
Livecycle-State [NORM] Active

Contents

  • Requirements definition
  • Architecture design (hardware, software, communication infrastructure)
  • Hardware design using VHDL and Verilog
  • Hardware implementation (FPGA)
  • Software design and implementation
  • System integration
  • Verification and test

Literature

  • Textbook: Marilyn Wolf, “Computers as Components -- Principles of Embedded Computing System Design “, Elsevier.
  • Textbook: David Patterson and John Hennessy, “Computer Organization and Design - The Hardware Software Interface”, Elsevier.

Materials

Manuals, data sheets and reference materials for the employed experimentation platform will be made available during the course.

Registration

Online registration required (see KIS)

Requirements for attendance (informal)

RTL design with VHDL or Verilog

Modules:

Requirements for attendance (formal)

None

References to Course [EIT-EIS-521-K-7]

Module Name Context
[EIT-EIS-521-M-7] Embedded Systems Laboratory P: Obligatory 4L, 5.0 LP